1. Field of the Invention
The present invention relates to a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Background Art
In manufacturing a semiconductor device, the step of selectively forming an impurity region in a semiconductor substrate is required. For example, in manufacturing an n-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in order to obtain an npn structure, the step of partially forming a p-type impurity region in an n-type semiconductor substrate and further partially forming an n-type impurity region in this p-type impurity region is often performed. Namely, two impurity regions different in extension from each other are formed. In a case where a silicon substrate is employed, since extension of an impurity region can be adjusted by diffusion, a double diffusion technique utilizing this feature has widely been used. Meanwhile, in a case where a silicon carbide substrate is employed, a diffusion coefficient of an impurity is small and hence it is difficult to adjust extension of an impurity region by diffusion. Namely, a region into which ions have been implanted becomes an impurity region substantially as it is through activation annealing. Therefore, the double diffusion technique cannot be employed. Thus, for example according to Japanese Patent Laying-Open No. 6-151860 (Patent Literature 1), ions are implanted by using a gate electrode having an inclined surface at an end surface as a mask. By utilizing the fact that a range of impurity ions in ion implantation can be controlled by an acceleration voltage, a desired impurity region is formed.
In the method above, extension of an impurity region is largely dependent on accuracy in formation of an inclined surface of a gate electrode, and hence error in extension of the impurity becomes great.